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Latest posts
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Chip Industry Technical Paper Roundup: Nov. 3
Meter-scale quantum interconnects; 2.5D/3D GPU integration and embodied emissions; secure memory-dependent prefetching; routing-aware analog placement; AI-enhanced flip-chip defect detection; superposed PCM for neural-network vector storage. The post Chip Industry Technical…
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AI Image Enhancement Improves Detection Of Flip-Chip Interconnect Defects (MCL, PVA TePla, ASE)
Researchers at Materials Center Leoben, PVA TePla, and Advanced Semiconductor Engineering (ASE) published “AI-Based Image Enhancement Improves Detection of Interconnect Defects in Microelectronic Packaging.” Abstract Excerpt: “Traditional failure-analysis (FA) methods face…
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3D Integration Reduces Embodied-Emissions Impact Of GPU Scaling (imec, VUB)
Researchers at imec and Vrije Universiteit Brussels published “Embodied Emissions of 2.5D and 3D Scaling in Chipletized GPUs for Low-Carbon AI.” Abstract “GPU compute resources are scaling to support growing AI workloads, leading to further rises in the climate change impact of…
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Quantum Interconnects Link Two 120-Qubit Processors (IBM Research)
Researchers at IBM Research published “Meter-scale quantum interconnects between large quantum processors.” Abstract Excerpt: “Modular quantum architecture requires long-distance quantum interconnects to stitch together individual processor modules. Such interconnects,…
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Hardware Defense Blocks Memory-Dependent Prefetcher Leakage (KU Leuven)
Researchers at KU Leuven and EURECOM published “SecDMP: Provably Secure Data Memory-Dependent Prefetching.” Abstract Excerpt: “In this work, we address this gap by designing a defense that is both secure and efficient. First, we propose a classification of DMP leakage,…
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Co-Optimizing Access Points Improves Analog Placement (UT Austin)
Researchers at the University of Texas at Austin published “APPlace: Co-Optimizing Device Locations and Access Points for Routing-Aware Analog Placement.” Abstract “Analog layout automation remains challenging in Analog/Mixed-Signal circuit design, because parasitics and…
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Shift Left Is Becoming A System-Level Problem
Rise in complexity is pushing engineers to validate hardware, software, and physical constraints earlier in the design flow, but fragmented workflows make that difficult. The post Shift Left Is Becoming A System-Level Problem appeared first on Semiconductor Engineering .
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Putting AI To The Test
Who verifies the verifier? This is the age-old question for anyone involved in the verification of semiconductor systems. Who verifies AI? The post Putting AI To The Test appeared first on Semiconductor Engineering .
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Chip Industry Week In Review
Marvell to buy Lumentum; HBM shortages threaten AI expansion; TSMC weighs price hikes; advanced packaging ramps; domain-specialized AI models; Infineon and UMC boost fab investments; Intel's quantum move; Lam and imec advance 3D integration; Google expands TPUs; AI-driven…
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Auto-Generation Of Properties: Methodology Insertion
Technology is only useful if it improves an existing methodology. Property generation is still refining that goal, but in the long term it could be very useful. The post Auto-Generation Of Properties: Methodology Insertion appeared first on Semiconductor Engineering .
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Rethinking Shift Left In Chip Design
Is it better to do everything earlier in the flow, or should design be more flexible and iterative? The post Rethinking Shift Left In Chip Design appeared first on Semiconductor Engineering .
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AI Raises The Bar For Tomorrow’s Engineers
Universities are redesigning curricula and assessments around judgment, validation, and technical depth. The post AI Raises The Bar For Tomorrow’s Engineers appeared first on Semiconductor Engineering .
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The Complexity Between The Bits
What biological reasoning can teach us about verifying silicon systems. The post The Complexity Between The Bits appeared first on Semiconductor Engineering .
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Is It Getting Hot In Here? Why Thermal Is No Longer A Signoff Problem
Applying the appropriate level of simulation and abstraction at each stage of the design process is key to effective thermal analysis. The post Is It Getting Hot In Here? Why Thermal Is No Longer A Signoff Problem appeared first on Semiconductor Engineering .
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Physics-Based Validation: The Foundation Of Trustworthy Agentic EDA
What self-verifying agents validate their decisions against and why physics-based engines are the authority on correctness. The post Physics-Based Validation: The Foundation Of Trustworthy Agentic EDA appeared first on Semiconductor Engineering .
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The EU Cyber Resilience Act Reaches Chip And IP Suppliers
Determining which products may fall within the CRA's scope and what information may need to be provided to customers. The post The EU Cyber Resilience Act Reaches Chip And IP Suppliers appeared first on Semiconductor Engineering .
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From Functional Monitoring To In-System Test: Extending Voltage-Aware Observability
Separate false failures caused by voltage droop from real structural defects. The post From Functional Monitoring To In-System Test: Extending Voltage-Aware Observability appeared first on Semiconductor Engineering .
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Scaling Autonomous Root Cause Analysis For Regression Triage
Solving difficult bugs while intelligently deciding what to investigate, what to rerun, and where to spend compute. The post Scaling Autonomous Root Cause Analysis For Regression Triage appeared first on Semiconductor Engineering .